The present invention relates to a method of manufacturing a semiconductor device. For example, the invention can be used for a method of manufacturing a semiconductor device having a nonvolatile memory.
A memory cell, which has a charge trapping insulating film sandwiched by oxide films below a gate electrode of a MISFET, is widely used as a semiconductor device having a memory cell of a nonvolatile memory that is electrically writable and erasable. The memory cell is referred to as metal oxide nitride oxide semiconductor (MONOS) type cell including a single-gate type cell and a split-gate type cell, and is used as a nonvolatile memory of a microcomputer.
A transistor including a metal gate electrode and a high dielectric constant film (high-k film) is increasingly used in a logic circuit portion along with a reduction in power consumption and/or speedup of the microcomputer. A so-called gate last process is known as a method of forming such a transistor, in which a source region and a drain region are formed using a dummy gate electrode including a polycrystalline silicon film formed on a substrate, and then the dummy gate electrode is replaced with a metal gate electrode.
Specifically, the transistor having the dummy gate electrode is covered by an interlayer insulating film, and then a top of the interlayer insulating film is polished to expose a top of the dummy gate electrode. Subsequently, the dummy gate electrode is removed, and a resultant space is filled with a metal gate electrode, resulting in formation of a MISFET having the metal gate electrode. At this time, an O3-TEOS film having a good gap filling characteristic is used as an interlayer insulating film filling between the adjacent dummy gate electrodes.
Japanese Unexamined Patent Application Publication No. 2001-244264 discloses a TEOS film having an improved gap filling characteristic between interconnection patterns.